Apparatus for classifying and counting sheets

ABSTRACT

Apparatus for classifying and counting sheets, post cards for examples, comprises a conveyor for conveying the sheets; a gate associated with the conveyor for deflecting the sheets away from the conveyor; sheet detecting means associated with the conveyor for generating a signal when it detects the sheet; a plurality of receivers for receiving sheets of different classes; check means for determining the classes of the sheets and for generating classification signals; gate driving means responsive to the classification signals and to the signal generated by the sheet detecting means; a first counter associated with the receivers for counting the number of sheets collected in respective receivers; a second counter which adds the number of sheets collected in respective receivers; a comparator for comparing the sum of the numbers of the sheets counted by the second counter with a preset number for determining whether the sum and the preset number coincide with other or not; a third counter for counting the number of wheets counted by the first counter and collected in respective receivers when the comparator determines that the sum coincides with the preset number; counting control means for controlling the second and third counters; and timing means for timing the operation of the third counter.

United States Patent 1 Mizunuma 51 Jan. 16, 1973 [75] Inventor: Yoshiyuki Mizunuma,

Japan [73] Assignee: Tokyo Shibaura Electric Co., Ltd.,

Kawasaki-shi, Japan [22] Filed: Nov. 9, 1971 [21] Appl. No.: 196,895

Kanagawa,

[30] Foreign Application Priority Date 250/219 WD, 219 LG, 219 TH; 340/259; 93/93 C; 271/56, 57

[56] References Cited UNITED STATES PATENTS 3,180,122 4/1965 Evans et al. ..209/82 X Primary Examiner-Allen N. Knowles Assistant Examiner-Gene A. Church AttorneySolon B. Kemon et a1.

L) 3 i s CHECK D 6 CIRCUIT i I II [57] ABSTRACT Apparatus for classifying and counting sheets, post cards for examples, comprises a conveyor for conveying the sheets; a gate associated with the conveyor for deflecting the sheets away from the conveyor; sheet detecting means associated with the conveyor for generating a signal when it detects the sheet; a plurality of receivers for receiving sheets of different classes; check means for determining the classes of the sheets and for generating classification signals; gate driving means responsive to the classification signals and to the signal generated by the sheet detecting means; a first counter associated with the receivers for counting the number of sheets collected in respective receivers; a second counter which adds the number of sheets collected in respective receivers; a comparator for comparing the sum of the numbers of the sheets counted by the second counter with a preset number for determining whether the sum and the preset number coincide with other or not; a third counter for counting the number of wheets counted by the first counter and collected in respective receivers when the comparator determines that the sum coincides with the preset number; counting control means for controlling the second and third counters; and timing means for timing the operation of the third counter.

24 Claims, 17 Drawing Figures SHEET BUNDLE CLASSIFICATION DUPLICATE AUDI TION PHI: VhN I ING MF ANS CONTROL DEVILt PATENTEDJAH 16 I973 3.710.936

SHEET 0 HF 12 ouT ouT ouT ouT Cp1 J Q P FF RESET FROM ONE LOT COUNT NUMBER F l EET DEVICE FIG. 1E

CLOCK PULSE COQUZNTER (106) 161 164 110 162 163 (07) 170 TO DELAY 165 CIRCUIT 16B 169 COUNTER PATENTEDJAN I 6 I973 3, 7.1 0.936

SHEET 05 0F 12 F I G. 2

O i CHECK CIRCUIT (6) L J TERMINAL l TTERMINAL lk [b J-KFF(50) KTERMlNAL L .l

9 OUTPUT 1 F? TERMINAL DETECTOR (14) [li U! DIFFERENTIAL NOT I e Mn cIRcuIT (16) h SWITCHING cIRcuIT (55) L] j 'JTERMlNAL TTERMINAL FF" J-KFF(52) k KTERMINAL l S l $255M 'J TERMINAL p f"? TTERMINAL L J-KFF(58) I K TERMINAL v L OUTPUT (1) 7! TERMINAL DETECTOR (28) 4] DIFFERENTIAL NOT m cIRcuIT (30) PATENTEU JAN 16 I973 SHEET [NM 12 hum mm I I 1 I l E3 wa mm F 70.22%? m k P 1 r MEG mm o N5 wm F W 79258;

T. Q w m wJoZDm uJoznm mom mom son mom mOm PATENTEDJAN 16 I975 3.710.936

SHEET U8 OF 12 F l G. 48

FROM SHEET DETECTOR F I G. 4C

I 5 1 ALARM DEVICE R 0 GATE 325 DRIVE DELAY CIRCUIT PATENTEDJAN I6 1975 3.710.936

SHEET 1101 12 FIG. 68

MM BOUT ouT DOUT 4 421 O 422 423 P s c,c s c c 8 1 2 1 1 2 i 'z gi g iz lg 429 431 52 RESET 0 o 6 m BIN ,CIN DIN FROM SUBTRACTER 410 F 6C TO SUBTRfCTER 41o AQUT BOUT ouT DOUT,

440 j 441 j 442 j 443 j Q Q Q Q 425 426 428 430 432 STROBIZ24 427 429 431 RESET 0 Am BIN CIN IN F I FROM ADDER 40s PATENTEDJM 16 1975 SHEET 12UF 12 FIG. 60

FIG. 6E

APPARATUS FOR CLASSIFYING AND COUNTING SHEETS This invention relates to apparatus for classifying and counting articles in the form of sheets such as post cards, paper movies, securities and the like and more particularly to such apparatus which classifies a lot of sheets of different types, counts the number of classified sheets for each type and then send them to individual receivers.

Throughout the specification and claim, the term sheet is used to mean not only a sheet shaped article but also an article of any configuration that can be processed by the apparatus of this invention.

The classifying and counting apparatus of the type referred to above is generally constructed to successively check the sheets supplied by from a magazine or reservoir for generating classification signals corresponding to the types of the sheets, classify and counts the sheets and then send the classified sheets to respective receivers in accordance with the classification signals. However, if two overlapped sheets are derived out from the reservoir, onlyone sheet is checked so that two sheets are sent to the same receiver and the not checked sheet will be classified inadvertently. Especially, where the sheets are divided into several lots and the sheets of each lot is classified, upon occurence of the erroneous classification, it is impossible to know which one of the lots was classified inadvertently by merely checking the cheets in individual receivers so that the result of classification and counting is not reliable.

Accordingly, it is an object of this invention to eliminate this disadvantage.

It is a feature of this invention to judge whether the number of sheets in one lot coincides or not with the sam of sheets which are classified and actually counted and sent to various receivers when the classification of the sheets of one lot is completed, and coincidence is obtained each time the classification of one lot is completed, the number of sheets classified in respective receivers is cummulutively added for each receiver, whereas in the case of uncoincidence the particular lot is classified again thus correcting the results of classification and counting. I

Another object of this invention is to provide an efficient classififying counting apparatus capable of classifying and counting sheets at high accuracies and can indicate the number of sheets classified and received in respective receivers when all sheets of several lots are completely classified and counted.

According to this invention there is provided apparatus for classifying and counting sheets comprising, (1) conveyor means for conveying the sheets in a predetermine direction, (2) a gate positioned at an intermediate point of the conveyor means for deflecting the sheets away from the predetermined direction, (3) sheet detecting means positioned at an intermediate point of the conveyor means for generating a signal when it detects the sheet, (4) a plurality of classification receivers adapted to receive sheets of different classes conveyed by the conveyor means, (5) check means for determining the classes of the sheets which are to be received in the corresponding classification receivers, the check means generating classification signals corresponding to the classes, (6) gate driving means responsive to the classification signals and to the signal generated by the sheet detecting means, (7) first counting means associated with the classification receivers for counting the number of sheets collected in the respective classification receivers, (8) second counting means for adding the numbers of the sheets collected in the respective classification receivers, (9) a comparator for comparing the sum of the numbers of the sheets counted by the second counting means with a preset number of sheets for determining whether the sum and the preset number coincide with each other or not, (IO) third counting means of the number equal to the number of the classification receivers for counting the number of sheets counted by the first counting means and collected in the respective classification receivers when the comparator determines that the sum coincides with the preset number, (11) count control means for controlling the operation of the second and third counting means, and, (12) timing means for timing the operation of the third counting means.

The present invention can be more fully understood from the following detailed description when taken in conjunction with reference to the appended drawings, in which:

FIGS. 1A, 1B and 1C, when combined together, show a block diagram of one embodiment of this invention;

FIGS. 1D, 15 and IF show detailed constructions of various circuit elements shown in FIGS. 1A, 1B and 1C;

FIGS. 2 and 3 show waveforms for explaining the operation of the apparatus shown in FIGS. 1A, 1B and 1C; 1

FIG. 4A shows a block connection diagram ofa sheet bundle classification control circuit shown in FIG. 1A;

FIGS. 48 and 4C show detailed connection diagrams of the circuit elements employed in the circuit shown in FIG. 4A;

FIG. 5 shows a detailed block connection diagram of the coincidence confirmation display means shown in FIG. 18;

FIG. 6A shows a detailed block connection diagram of the fraction processing member shown in FIG. 1A;

FIGS. 68, 6C and 6D show block diagrams of circuit element employed in the fraction processing member shown in FIG. 6A; and

FIG. 6E shows a truth table for explaining the operation of the full adder sustractor shown in FIG. 6D.

Referring now to FIG. 1A of the accompanying drawing, there is provided a magazine or reservoir 1 from which sheets 2 such as post cards are sequentially supplied into conveyor belts 3. A suction chamber 4 is provided in front of reservoir 1 to sequentially attract successive sheets at a predetermined intervel. The attracted sheets are clamped between conveyor belts 3 and conveyed in a direction indicated by an arrow 5. Along the conveyor belts 3 is provided a check circuit 6 for checking characteristic items used to determine the features of the sheets 2 such as the length, width, thickness codes, masks, numerals and pattern printed thereon. When sheets belonging to a first class including those of a first class and those not classified as the second and third class to be described later are classified into first receiver 7, the check circuit 6 applies a predetermined classification signal corresponding to the first class to a classification signal conductor 7a, whereas applies a classification signal corresponding to the second class to a classification signal conductor 90 when the sheets belonging to the second class are classified into a second class receiver. Further, when the sheets belonging to the third class are classified into a third class receiver 11 the check circuit 6 applies a corresponding classification signal to a classification signal conductor 11a. A first detector 14 including an electric lamp l2 and a photoelectric covering element l3on the side of the conveyor belts 3 opposite the lamp 12 is located on the downstream side of the check circuit 6. First detector 14 produces a negative detection signal which becomes zero when the light from lamp 12 is intercepted by the sheet. The detection signal is applied to a differential NOT circuit 16 through an amplifier 15. Behind the first detector 14 is provided a tiltable first gate 17. When the gate 17 is positioned in the solid line position the sheets are conveyed straight forwardly whereas when the gate is positioned in the dotted line position, the sheets are conveyed in the direction of arrow 20 by the action of a first branching belt 19 thus correcting the sheets of the glass in the receiver 7. Associated with the first branching belt 19 is a second detector 23 comprising an electric lamp 21 and a photoelectric converting element 22 for detecting the sheets of the first class deflected towards receiver 7. The signal generated by the second detector 23 is applied to counter via an amplifier 24 to count the number of sheets deflected to receiver 7. Elements 23, 24 and 25 constitute first counting means.

To the next of the first gate 17 is provided a third detector comprising a lamp 26 and a photoelectric converting element 27 for providing a signal to a differential NOT circuit 30 and a NOT circuit 31 through an amplifier 29. On the output side of the third detector 28 is located a tiltable second gate 32. When this gate is positioned in the solid line position the sheets are conveyed straight forwardly as shown by arrow 5, whereas in the dotted line position, the sheets of the second class are conveyed in the direction of arrwo 34 towards receiver 9 by the action ofa second branching belt 33. A fourth detector 37 comprising a lamp 35 and a photoelectric converting element 36 is associated with the second branching belt 33 for detecting the sheets of the second class. The signal generated by the forth detectro 37 is applied to a counter 39 via an amplifier 38 for counting the number of sheets deflected to receiver 9. The sheets 2 of the third class that have passed straight forwardly over the second gate 32 are collected in a receiver 11. The' sheets directed to receiver 11 are detected by a fifth detector 42 comprising a lamp 40 and a'photoelectric converting element 41 and the output signal from the fifth detector 42 is supplied to a counter 44 for counting the number of sheets of the third class directed. to receiver 1 l.

The classification signal applied to conductor 9a is supplied to a J terminal of the J K flip-flop circuit 50 (hereinafter designated as J KFF) of a gate driving circuit and also to the K terminal of the J KFF via a NOT circuit 51. In the same manner, the classification signal on conductor 7a is supplied to the J terminal of another J KFF 52 of the gate driving circuit and to the K terminal of the same J KFF through a NOT circuit 53. The I terminals ofJ KFFs 50 and 52 are supplied with the output signal from the first detector 14 through the differential NOT circuit 16. Each of the J KFFs is constructed such that when a l signal is applied to T terminal concurrently with the application of a l signal upon J terminal it will produce a l signal on the output terminal 1, whereas when a 1" signal is applied to T terminal concurrently with the application of a 1 signal upon K terminal it will produce a 0 signal on the output terminal 0. When the sheets of the first class passes through detector 14 immediately after they have been checked by detector 6, the signal appearing at the output terminal 1 ofJ KFF 50 is supplied to a switching circuit 55 through amplifier 54. Upon receiving a 1" signal switching circuit 55 operates to supply a current from a DC source 56 to a first gate driving relay 57. The first gate 17 is held in the solid line position by means of a spring, not shown, in the absence of any input to the gate driving circuit. However, when the first gate driving relay 57 is energized gate 17 is tilted to the dotted line position to collect the sheets of the first class in receiver 7. Signals produce at the terminals 1 and 0 ofJ KFF 52 are applied to terminals J and K ofJ KFF 58 while the output signal from the third detector 28 is supplied to the terminal K ofJ KFF 52 via amplifier 29, NOT- circuit 31 and differential NOT circuit 59. The output from the third detector 28 is also applied to the terminal T of J KFF 58 via amplifier 29 and differential NOT circuit 30. When the sheets of the second group are conveyed, check circuit 6 and detector 28 successively produce output signals and the output produced on output terminal 1 of J KFF 58 in response to these output signals is supplied to a switching circuit 60 via an amplifier 59. Like the switching circuit 55, when supplied with a l signal, switching circuit 60 passes a current from DC source 56 through a relay 6] for dri'ving the second gate 32. Like the first gate 17, the second gate 32 is normally held in the solid line posi tion but is moved to the dotted line position when relay 61 is energized to collect the sheets of the second class in receiver 9. The sheets of the third class are conveyed into receiver 11.

Circuit elements described above operate to take out the sheets 2 from the reservoir, or magazine check, classify them into respective receivers and count the number of sheets collected in respective receivers.

FIG. 1C shows a block connection diagram of a circuit constructed to check whether the predetermined number of the sheets of one lot coincides or not with the number of sheets actually detectected as they are classified into respective receivers when the classification of the sheets of the lot has been completed, and

'upon coincidence the circuit operates to cummulatively counts the number of sheets collected in each receiver when the classification of the sheets of the lo is completed.

More particularly the outputs from counters 25, 39 and 44 shown in FIG. 1B are supplied to comparators 80, 81 and 82, respectively, shown in FIG. 1C. Outputs from these comparators are supplied to NOT circuits 83, 84 and 85 respectively. Further, the output from comparator is applied to the input terminal a of a two input NAND circuit 86, the output from comparator 81 is applied to the input terminal a ofa three input NAND circuit 87 and the output from ocmparator 82 is applied to the input terminal a of a three input NAND circuit 88. The outputs from the two input NAND circuit 86 and three input NAND circuits 87 and 88 are supplied to clock pulse counters 92, 93 and 94, respectively, through NOT circuits 89, 90 and 91 and the outputs from these clock pulse counters are applied to the other inputs of the comparators 80, 81 and 82, respectively. Comparators 80, 81 and 82 operate to respectively compare the contents of counters 25, 39 and 44 with the contents of counters 92, 93 and 94. When these contents coincide with each other, comparators produce 0 outputs whereas in the case of uncoincidence the comparators produce 1 outputs respectively. The outputs from NOT circuits 83, 84 and 85 are supplied to the input terminals a, b and 0, respectively of a three input NAND circuit 95. Further the output from NOT circuit 83 is supplied to the input terminal b of the three input NAND circuit 87, whereas that from NOT circuit 84 is applied to the input terminal b of the three input NAND circuit 88. The clock pulse from a clock pulse generator 96 is applied to the input terminals c of three input NAND circuits 87 and 88 to the input terminal b of two input NAND circuit 86 through a two input NAND circuit 97 which operates to produce a signal similar to the clock pulse in response to the clock pulse supplied from the clock pulse generator 96 only when a l signal is applied to the input terminal b of two input NAND circuit 97. On the other hand, the three input NAND circuits 87 and 88 produce outputs on their output terminals corresponding to the signals impressed upon their input terminals c only when l signals are applied on their input terminals a and b but produce 1" outputs when 0 signals are applied to their input terminal a or b. The two input NAND circuit 86 and the three input NAND circuits 87 and 88 constitute a clock pulse prohibiting means, and as above described the outputs from these NAND circuits are supplied to NOT circuits 89, 90 and 91 respectively, to the respective input terminals a, b and c of the three input NAND circuit 98 and to the respective input terminals a of two input NAND circuits 99, 100 and 101, respectively. The outputs from respective two input NAND circuits 99, 100 and 101 are applied to addition counters 120, 130 and 140, respectively, which are provided for respective receivers 7, 8 and 9. The output from the three input NAND circuit 98 is applied to the input terminal a of a two input NAND circuit 102. The other input terminal of this NAND circuit is connected to receive an output signal produced on the output terminal 1 of a set-reset type flip-flop circuit 103 (hereinafter designated as S- RFF). The S-RFF 103 is normally held in the reset condition to produce a 0 signal on its output terminal 1 and a l signal on its output terminal 0. When a stop signal is applied, manually or automatically, on the set terminal S upon completion of the classification of the sheets of one lot, the S-RFF 103 is changed to 'the set condition to produce a 1" signal'on its output terminal 1 and a 0 signal on its output terminal 0. The output from above described two input NAND circuit 102 which receives at its inputs the outputs from S-RFF 103 and three input NAND circuit 98 is applied to a summation counter 104 and the output from this counter is applied to a sum comparator 105. The summation counter 104 counts the'sum of the sheets of respective classes classified into respective receivers 7, 9 and 11,

25, 39 and 44 when the classification of the sheets of one lot is completed. The sum comparator 105 functions to compare the number of sheets of one lot preset therein with the result of the summation counter 104 to determine whether they coincide with each other or not thus producing a coincidence signal only when a coincidence is obtained. The output from the three input NAND circuit is supplied to an input of sum comparator 105 through a NOT circuit 106 and an AND circuit 105A so that the the sum comparator 105 operates to compare when the output from three input NAND circuit 95 is zero, that is when a l signal is applied to sum comparator and a l signal from the output terminal 0 of .l-KFF 107 is applied to the sum comparator via AND circuit 105A. The coincidence output from sum comparator 105 is delayed a definite time by a delay circuit 1 10 consisting of monostable multivibrators 108 and 109 and the delayed signal is then applied to the terminal T ofj-KFF 107. Monostable multivibrators 108 and 109 are normally maintained in this reset conditions to produce 0 signals on their output terminals 1 and l signals on their output terminals 0. When the coincidence output is applied, the monostable multivibrator 108 is changed to the set condition thereby producing a l signal on its output terminal 1 and a 0 signal on its output terminal 0. The monostable multivibrator 109 is reset by the trailing edge of the signal produced at the output terminal 1 of the preceding monostable multivibrator 108. The output terminal 1 of .l-KFF 107 is connected to its K terminal and the output terminal 0 is connected to its J terminal so that the J-KFF 107 is normally maintained in the reset condition to produce a 0" signal on its output terminal 1 and a 1 signal on its output terminal 0. Under the reset condition, when a 1 signal is supplied to terminal T, the .l-KFF 107 is changed to the set condition thereby producing a l signal on its output terminal 1 and a 0 signal on its output terminal 0. The signal appearing at the output terminal 0 of the J-KFF 107 is also supplied to the input terminal b of a two input NAND circuit 111. Input terminal a of this NAND circuit 111 is connected to receive the signal produced at the output terminal 0 of the S-RFF 103 and the output of the NAND circuit 111 is applied to the input terminal b of NAND circuit 97. NAND circuit 97, S-RFF 103, J-KFF 107 and NAND circuit 111 constitute a clock pulse pass control means. The signal produced at the output terminal of J-KFF 107 is applied to respective input terminals b of the NAND circuits and 101 as well as to the input terminal b of the two input NAND circuit 112. Further, the output from NAND circuit 106 is applied to the input terminal a of NANDv circuit 106 while the 0 output signal from this NAND circuit 112 is supplied to the reset terminal K of J-KFF 107 thus resetting the same. The 0 output from NAND circuit 112 is also supplied to summation counter 104 for resetting its content to zero. Furthermore, the 0 output signal from NAND circuit 112 is applied -to various counters 25, 39 and 44, thereby resetting the contents thereof to zero. The output from NAND circuit 112 is applied to the input terminal a of two input NAND circuit 1 13, the other input terminal b thereof being connected to receive the output signal counters 92, 93 and 94 via a NOT circuit 114 thereby resetting to zero the contents of these counters when NOT circuit 114 produces an output signal. The signal appearing at the output terminal 0 of the monostable multivibrator 108 of delay circuit 110 is applied to the reset'terminal R of S-RFF 103 so that when a 0" signal is produced at the output terminal 0' the S-RFF 103 is reset. Where the sum comparator 105 does not produce a coincidence signal upon completion of the classification operation of the sheets of one lot, it is necessary to classify and count again the lot. For this purpose, circuit elements 110, 112, 113 and 1 l4 constitute a timing means for providing an external zero reset signal.

The scircuit elements described above operate to determine whether the predetermined number of the sheets of one lot coincides or not with the sum of the sheets actually classified and collected in respective receivers and when a coincidence is obtained, the above described circuit element cummulatively sum up the number of sheets collected in each receiver each time the classification operation of the sheets of each lot is completed, whereas in the case of uncoincidence, said circuit element reset to zero the contents of respective counters by applying an external zero resetting signal and reset respective flip-flop circuits thus classifying and counting the particular lot which was erroneously counted and classified. The NAND circuit utilized herein functions to provide a 0" output only when all inputs are 1. Further, although the operation of the logic circuits is explained herein in terms of the positive logic it is to be understood that the negative logic can also be used. For the negative logic it is necessary to change NAND to NOR, AND to OR and OR to AND.

FIG. 1D is a block connection diagram showing a binary coded decimal counter for one digit or order of magnitude utilized in counters 25, 39 or 44 shown in FIG. 18, clock pulse counters 92 to 94, or the summation counter 104 or addition counters 120, 130 and 140 forrespective receivers, shown in FIG. 1C. Each one digit of this counter is comprised by four bits utilizing a code l-2-4-8, each bit comprising flip-flop circuits 150 151, 152 and 153, respectively. The input pulse is applied to a terminal Cp Each one of the flip-flop circuits ,150 through 153 is constructed to be set by the trailing edge of the pulse impressed upon its terminal Cp to produce an output at terminals Aout to Dout. Flip-flop circuit 153 reverses its conditions when it receives an input at terminal Cp while a 1 input is being applied to input terminal S and a 0 input is applied to input terminal R thus changing the output from O to l The binary coded decimal counter shown in FIG. 1D operates as follows: First, it is assumed that all flip-flop circuits 150 to 153 have been cleared by the application of a reset signal. Upon application of a positive pulse upon input terminal Cp the flip-flop circuit 150 will be set by the trailing edge of the pulse thus producing outputs 0001 representing a decimal l at respective output terminals Aout to Dout. The next pulse resets the flip-flop circuit 150 to produce an output 0." The flip-flop circuit 151 is set by the trailing edge of the second pulse thus producing outputs 0010 representing a decimal 2 at output terminals Aout to Dout. The third input pulse sets the flip-flop circuit 150. However, the

condition of the flip-flop circcuit 151 will not be changed because of the absence of an input thereby producing outputs 001 1 corresponding to a decimal 3. Flip-flop circuits 150 and 151 are reset by fourth input while the flip-flop circuit 152 is set thus producing outputs 0100 corresponding to a decimal 4. When a pulse is applied to input terminal Cp when the outputs from output terminal are Ol l 1 (decimal 7), flip-flop circuits 150 to 152 will be reset. Since, at this time, the terminal R of flip-flop circuit 153 receives a 0 and the terminal S receives a l out signal of the flip-flop circuits 151 and 152, the flip-flop circuit 153 will be set producing outputs 1000 (decimal 8). In this manner, when flip-flop circuits 150 and 152 are reset while flipflop circuits 151 and 153 are set thus providing 1010 (decimal 10), the flip-flop circuit 153 will produce a carry signal. The eleventh pulse input issupplied to the input of the flip-flop circuit comprising the first bit of the next digit (one order higher). In the same manner, counting operations are successively performed for producing binary cod ed decimal outputs at respective output terminals Aout to Dout of respective orders of magnitude.

To use the counter shown in FIG. ID in counters 25, 25a, 39, 39a, 44 and 440 three counters shown in FIG. ID are used in each case so as to count three digits. The outputs from detectors 23, 37 and 42 to counters 25, 39 and 44 are respectively applied to the terminal Cp shown in FIG. 1D. In the same manner, clock pulse counters 92 to 94 shown in FIG. 1C function to apply the outputs from NOT circuits 89 to 91 to inputtermina1Cp,. The summation counter 104 applies the output from NOT circuit 102 to input terminal Cp while addition counters 120, and are connected to apply the outputs of NOT circuits 99, 100 and 101 upon input terminal Cp FIG. 1E shows a detailed connection diagram of one, for example 80, of comparators 80 to 82 shown in FIG. 1C. As shown, one bit of comparator 80 comprises two NOT circuits 161 and 162, two AND circuits 163 and 164 and one NOR circuit 165. Four bits constitute one comparator for one digit. Accordingly, where counter 25 and clock pulse counter 93 are constructed to count a numeral of three digits, for example, it is necessary to provide three such 1 circuits. For the sake of description, however, only one circuit is shown in FIG. 1E. Signals for respective bits of the least significant digit, for example, are applied to one input terminals of the NOT circuit 161 and AND circuit 163 of each bit whereas the signal from the clock pulse generator 92 is' applied to one input terminals of NOT circuit 162 and AND circuit 164. In this comparator, when 1 inputs are applied upon conductors 166 and 167, respectively, either one of NAND circuits 163 and 164 does not produce an output so that NOR circuit 165 provides a .l output. In the same manner, when the output from counter 25 or 92 is a l or 0 for respective bits, one of four NOR circuit 165 produces an output which is applied to a NOT circuit 168' via an AND circuit 168 thus producing a 0 output from NOT circuit 169 which means that the counted numbers concide with each other. Whenever a l or input is applied to one bit among four bits for one digit, the AND circuit 168 does not produce an output so that NOT circuit 169 will produce an output 1 thus indicating uncoincidence.

FIG. 1F shows a detailed connection digram of the sum comparator 105 shown in FIG. 1C. This circuit is substantially identical to that shown in FIG. 1B so that corresponding elements are designated by the same reference numerals. The inputs to be compared for respective bits are applied from summation counter 104 shown in FIG. 1C and from a one lot count number setter, not shown, which may be constituted by a counter identical to that shown in FIG. 1D. In FIG. 1F, an AND CIRCUIT 168 has five input terminals and to the fifth input terminals thereof are applied the outputs from NOT circuit 106 and J-KFF 107 via an AND circuit 170. The output from AND circuit 168 is applied directly to delay circuit 110 shown in FIG. 1C without being inverted. The AND circuit 170 is provided for each digit in order to simultaneously discriminate three digit binary coded decimal signals.

More particularly, with this sum comparator when all four NOR circuits 165 produce output 1, AND circuit 168 provides a coincidence signal for delay circuit 110 under the control of the output from AND circuit 170.

The embodiment described above operates as follows: The sheets 2 are successively derived out of the magazine 1 by the operation of suction chamber 4 and are then conveyed in the direction of arrow 5 at a definite spacing by means of conveyor belts 3. Each sheet is then checked of its configuration, width, length and thickness, etc., by means of check circuit to determine that the sheet should be collected in a particular one of the receivers. Assuming now that a sheet of the first class has been determined to be received input receiver 7, a 1 signal having a predetermined width as shown in FIG. 2A is applied to classification signal conductor 70 so as to apply a l signal upon the terminal J of J-KFF 50 and a 0" signal upon the K terminal of the same J-KFF as shown in FIG S. 2B and 2C. As the sheet checked by check circuit 6 passes through the first detect circuit 14 it will produce a detection Signal shown in FIG. 2D. The trailing edge of this detection signal (1 is differentiated by differential NOT circuit 16 to form a signal e which is applied upon the terminal T of J-KFF 50 as shown by FIG. 2F. Since ter-.

minal J of the JKFF 50 has been supplied with a 1 input, the J-KFF 50 will produce a 1" signal g at its output terminal 1 which is supplied to siwtching circuit 55 via amplifier 54. Responsive to this 1 signal, the switching circuit 55 is switches (shown by FIG. 2H) to supply current to gate driving relay 57 from DC source 56. Consequently, the first gate 17 is moved to the dotted line position to deflect the sheet in the direction of arrow 20 thus collecting the sheet in receiver 7. The sheets classified into receiver 7 aredetected by the second detector 23 and the number of the detected sheets is counted by the counter 25. The sheets subsequently classified into the receiver 7 are collected in the receiver and counted in the same manner.

Collection in receiver 9 is made as follows. The sheets of the second class conveyed by the converyor belts are checked by detector 6 which applies a 1" signal 1' on classification signal conductor 90, a 1" signal 1 (FIG. 2]) to the terminal J of J-KFF 52. As the sheets 2 checked by the check circuit 6 pass through detect circuit 14 this detect circuit 14 produces a detection signal (FIG. 2L). The trailing edge of the detection signal is differentiated by means of differential NOT circuit 16 to form a signal m which is applied to the terminal J of J-KFF 52, as shown by FIG. 2N. Since the 1 signal (FIG. 2J) has been applied to the terminal J of the J-KFF 52, this J-KFF produces a 1 signal (FIG. 20) at its output terminal 1 which is coupled to the terminal of the succeeding J-KFF 58 as shown by FIG. 2P. Simce the detection signal A from the first detector 14 is also applied to the terminal J of JKFF 50 via differential NOT circuit 16 (see FIGS. 2M and 26), the J-KFF so provides a signal to its output terminal 0 and a 0 signal to the output terminal 1. As a result, the first gate 17 is maintained in the solid line position thus advancing straight forwardly the sheets towards the third detector 28 in the direction of arrow 5. The third detector 28 produces a detection signal r as the sheet passes therethrough. This detection signal r is converted into a signal s by the action of the differential NOT circuit 30, which is supplied to terminal J of JKFF 58, as shown in FIG. 2T). Since a l signal has been applied to terminal J, the J-KFF 58 produces a l signal (FIG. 2U) at its output terminal 1 which is applied to switching circuit 60 via amplifier 59. Thus, the switching circuit 60 is switched by the l signal to energize gate driving relay 61 from DC source 56, thus moving the second gate 32 to the dotted line position to carry the sheets of the second class toward receiver 9. The sheets collected in the receiver 9 are detected by the fourth detector 37 and the number of the sheets is counted by counter 39.

When the sheets 2 are classified into receiver 11, the first and second gates 17 and 32 are held in their solid line positions so that the sheets are conveyed straight forwardly into receiver 11. More particularly, at this time too, detector 6 produces a 1 signal, but this signal is applied to only a counter 44a to be described later. Consequently, a 1" signal is supplied to the terminals K of J-KFF 50 and J-KFF 52 whereas a 0 signal is applied to the J terminals thereof. The signal from the first detector 14 is applied to terminals J of J-KFFs 50 and 52 to produce a l signal at the output terminal 0 of J-KFF 50. However, this output signal 1 is not supplied to switching circuit 55 so that the gate 17 will be held in the solid line position whereby the' sheets are advanced straight forwardly. The 1 signal appearing at the output terminal 0 of J-KFF 52 is coupled to the terminal K of J-KFF58. Since the detection signal from the third detector 28 is applied to terminal J of J-KFF 58, this J-KFF provides a l signal at its output terminal 0 but this 1" signal is not supplied to switching circuit 60. Consequently, the second gate 32 too is held in the dotted line position thus allowing the sheets of the third class to advance straight forwardly into receiver 11. The sheets collected in this receiver are detected by the second detector 42 and the number of these sheets is counted by the counter 44. The contents X X and X of counters 25, 39 and 44, respectively, are supplied to comparators 80, 81 and 82, respectively, shown in FIG. 1C.

When the classification operation of the sheets of one lot is completed as above described, stop signal 200 shown in FIG. 3 is applied, by a manual or an automatic operation, to the set terminal S of S-RFF 103 to produce'a signal 202 (see FIG. 3) at its output terminal 0. At this time, the J-KFF 107 is in the reset condition and an 1 signal 204 is being provided at its output terminal 0. As a result, NAND circuit 111 produces a 1" signal 205 which is supplied to NAND circuit 97. Since this NAND circuit 97 is supplied with the clock pulse 203 generated by clock pulse generator 96, it generates an output signal 206. Since at this time, comparator 80 produces a l signal 207, the NAND circuit 86 also produces an output identical to output 206. This signal is inverted by the NOT circuit 89 and is then counted bythe clock pulse counter 92, as shown by a curve 209-in FIG. 3. Concurrently therewith, the output from NAND circuit 86 is applied to the input terminal c of NAND circuit 98 and to the input terminal of NAND circuit 101. Since the output from NAND circuit 87 and the output from NAND circuit 88 which are applied to two input terminals of NAND circuit 98 are both the' NAND circuit 98 will produce an output corresponding to the signal supplied to its input terminal 0. Since the l signal 201 appearing at the output terminal 1 of S-RFF 103 is applied to the input terminal b of the NAND circuit 102 which follows NAND circuit 98, upon application of the output from NAND circuit 98 on its input terminal a, the NAND circuit 102 produces an output signal corresponding to the signal applied to its input terminal a and this output signal is counted by the summation counter 104, as shown by 208 in FIG. 3. Thus, concurrently with the commencement of the counting operation of the clock pulse counter 92, the summation counter 104 also starts to count. Although a signal is applied to NAND circuit 101, it will not produce any output signal since .l-LFF 107 produces a 0 output signal at its output terminal 1. When the content of the clock pulse counter 92 coincides with the content of the counter 25, comparator 80 will produce a 0 output signal 210. Accordingly, the NAND circuit 86 will produce 1 signals at its all output terminals even when a clock pulse 206 is supplied to its input terminal b and these 1" output signals are inverted into 0 signals by the operation of NOT circuit 89 so that clock pulse counter 92 becomes inoperative, as shown by a curve 211 of FIG. 3. Further, the 0 output signal 210 from comparator 80 is inverted into a l signal by the operation of NOT circuit 83 and is then supplied to the input terminal a ofNAND circuit 95 and also to the input terminal b of NAND circuit 87. Since the 1" output signal 212 from comparator 81 is supplied to the input terminal a of NAND circuit 37, upon application of the outputsignal 206 from NAND circuit 97 upon the remaining input terminal, the NAND circuit 87 will produce an output signal identical to signal 206, which is inverted by NOT circuit 90 and is counted by the clock pulse counter as shown by a curve 213 in FIG. 3. Also the output from NAND circuit 87 is supplied to NAND circuits 98 and 100. Since the output from NAND circuit 86 and the output from NAND circuit 88 which are supplied to two input terminals a and c of the NAND circuit 98 are both 1 signals, the NAND circuit 98 will produce an output corresponding to the output of NAND circuit 87. Responsive to this output, the NAND circuit 102 in the next stage will produce a similar signal which is counted by summation counter 104 as shown by curve 215 in FIG. 3. In this manner, in the same manner as above described, concurrently with the commencement of the counting operation of the clock pulse counter 93, the summation counter 104 also starts the counting operation. Although a signal is also supplied to NAND circuit 100 since a 0 output is produced at the output terminal 1 of .l-KFF 107, l signals are produced thereby producing no output signal. When the content of the clock pulse counter coincides with the content of counter 39, the comparator 81 produces a 0 output signal 216. As a result, even when a clock pulse 206 is applied to the input terminal c, the NAND circuit 87 will produce l signals at its all output terminals and these 1 signals are inverted into l signals by the operation of NOT circuit 90 thereby stopping the counting operation of the clock pulse counter 93, as shown by' curve 217. The "0" output signal from comparator 81 is inverted into a l signal by the operation of NOT circuit 84 and the inverted signal is applied to the input terminal b of NAND circuit 95 as well as to the input signal b of NAND circuit 88. Since the l output signal 218 from comparator 82 is applied to the input terminal a of NAND circuit 88, upon application of the output signal 206 from NAND circuit 97 on the input terminal 0, NAND circuit 88 will produce an output identical to the output signal 206 which is inverted by NOT circuit 91 and is counted by the clock pulse counter 94, as shown by curve 219. Further, the output from NAND circuit 88 is supplied to the input terminal a of NAND circuit 98 and the input terminal a of NAND circuit 99. Since two input terminals b and cof NAND circuit 98 receive l outputs from NAND circuits 86 and 87, in response to the output from NAND circuit 88, the NAND circuit 98 will produce a similar signal which is used to produce a similar signal from the succeeding NAND circuit 102. The signal produced by NAND circuit 102 is counted by the summation counter 104, as shown by curve 220. More particularly, in the same manner as above described, concurrently with the commencement of the counting operation of the clock pulse counter 94, the summation counter 104 also starts the counting operation. Although a signal is also supplied to NAND circuit 99, since the output from the output terminal 1 of J-KFF is a 0 signal, only 1 signals are produced thus producing no pulse signal. As above described, when the content of clock pulse counter 94 coincides with the content of counter 44, the comparator 82 produces a 0" output signal 221. Consequently, even when a clock pulse is applied to the input terminal c, the NAND circuit 88 will produce only 1" signals which areinverted into 0 signals by the action of NOT circuit 91 whereby the operation of the clock pulse counter 94 is stopped as shown by curve 222.

In this manner, the summation counter 104 counts the total sum of the numbers of sheets classified into respective receivers 7, 9 and 11 and the content of the summation circuit is applied to sum comparator 105. At this time, 1 signals are applied to all input terminals a, b and c of NAND circuit 95 so that this NAND circuit will produce a 0 output signal which is inverted into 1 signal 292 by the action of NOT circuit 106 to be applied to the sum comparator 105. Furthermore, as the sum comparator 105 receives the 1 signal from the output terminal of J-KFF 107, the sum comparator 105 operates to determine whether the content of summation counter 104 coincides or not with the predetermined number of the sheets of one lot. When a coincidence is obtained sum comparator produces a coincidence signal 0" 230. The trailing edge of the concidence signal 0 sets the monostable multivibrator 108 in the first stage of delay circuit 110 to generate a 0 signal 231 at its output terminal 0 which is applied to one input terminal b of NAND circuit 113. At the same time, this signal 231 is applied to the reset terminal R of S-RFF 103 to reset the same by the build-up edge of the signal. Since the 0 output signal from NAND circuit 112 is impressed upon the other input signal of NAND circuit 113, this NAND circuit will produce a 1" signal which is inverted into a 0 signal by the action of NOT circuit 114 thus resetting counters 92, 93 and 94 to zero. Upon resetting to zero, respective comparator 80, 81 and 82 will produce again 1 signals as shown by curves 250, 251 and 252, respectively, and these l signals are inverted into 0" signals by the action of respective NOT circuit 83, 84 and 85 to be supplied to the NAND circuit 95. When reset, the S-RFF 103 produces a 1 signal at its output terminal 0 so that NAND circuit 111 will produce a 0 signal 253 to maintain a 0 signal at the output terminal of NAND circuit 97, as shown by curve 253.

The monostable multivibrator 109 in the next stage is set by the trailing edge 237 of the signal 236 generated at the output terminal 1 of the monostable multivibrator 108 and the leading edge 239 of the output signal from the monostable multivibrator 109 is applied to the terminal J of J-KFF 107 thus causing it to produce a l signal 240 at its output terminal 1 and a 0 signal at its output terminal 0. Consequently, NAND circuit 111 will produce again a l signal 242 since its inputs a and b are supplied with signals 1" and 0 respectively, so that NAND circuit 97 will produce a signal 245 at its output terminal corresponding to the clock pulse 203. Signal 245 is counted (as shown by 246), again by the clock pulse counter 92 through NAND circuit 86 and NOT circuit 89 as above described and also by summation circuit 104 as shown by curve 280. The output from NAND circuit 86 is also supplied to the input terminal a of NAND circuit 101. Since the input terminals b of these NAND circuits 101, 100 and 99 are supplied with the 1 signal 240 appearing at the output terminal 1 of .l-KFF 107, the summation circuit 104 also begins to count as shown by curve 290.

When the contents of clock pulse counter92 and counter 25 coincides with each other, the comparator 80 applies a 0 signal 255 to the input terminal a of NAND circuit 86 thus causing it to produce a 1 signal at its output terminal so that the counting operations of the clock pulse counter 92 and the addition counter 140 are terminated, as shown by curves 281 and 282.

As above described, the 0 output signal 255 from comparator 80 is inverted into a l signal by NOT circuit 83 which is then supplied to the input terminal a of NAND circuit 95 and to the input terminal b of NAND circuit 87. Consequently, this NAND circuit 87 produces an output corresponding to signal 245 so that clock pulse counter 93 and summation counter 104 resume their counting operations as shown by curves 283 and 284. At this time, since the output from NAND circuit 87 is also supplied to the input terminal a of addition counter 130, this counter commences its counting operation as shown by curve 285.

As above described, when the contents of clock pulse counter 93 and counter 39 coincide with each other, the comparator 81 will provide a 0 signal 261 to the input terminal a of NAND circuit 87 to cause it to generate a 1 signal its output terminal thus terminating the counting operations of the clock pulse counter 93 and addition counter 130 as shown by curves 259 and 260.

Further, as above described, the 0 output signal 261 from comparator 81 is converted into a l signal for application to the input terminal b of NAND circuit 95 as well as to the input terminal b of NAND circuit 88.

When supplied with a l signal to the input terminal b, the NAND circuit 88 produces an output corresponding to signal 245 thereby causing the clock pulse counter 94 and the summation counter to resume their counting operations, as shown by curves 262 and 263. The output from the NAND circuit 89 is also supplied to addition counter 120 thus causing it to commence the counting operation as shown by curve 264. As above described, when the contents of clock pulse counter 94 and counter 44 coincide with each other the comparator will apply a 0 signal 291 upon the input terminal a of NAND circuit 88 thereby terminating the counting operations of the clock pulse counter 94 and addition counter as shown by corves 265 and 266. As a result, addition counters 120, and will store the same number of counts as those of counters 25, 39 and 44 respectively.

Since 1" signals are reapplied upon the input terminals a, b and c of NAND circuit 95, this NAND circuit produces a 0" signal at its output terminal which is inverted into a 1 signal 267 by NOT circuit 106 and is then applied to the input terminal a of NAND circuit 112 and to the sum comparator 105. Since J-KFF produces a 0 signal 241 at its output terminal 0, the sum comparator 105 does not operate to produce a coincidence signal. However, as the 1 signal 240 appearing at the output terminal 1 of J-KFF 107 is applied to the input terminal b of NAND circuit 112, this NAND circuit produces a 0 output signal which is utilized to reset to zero the contents of summation counter 104 and respective counters 25, 39 and 44. Further, the 0" output signal of NAND circuit 112 resets J-KFF 107 to cause it to generate a l signal 270 at its output terminal 0 and a 0 output signal 271 at its output terminal 1. Consequently NAND circuit 111 produces again a 0 output signal 293. Further, the 0 output signal from NAND circuit 112 is impressed upon the input terminal a of NAND circuit 113. Since the l signal 272 appearing at the output terminal 0 of the monostable multivibrator 108 is impressed upon the input terminal b of NAND circuit 113, this NAND circuit produces a 1 output signal which is inverted into a 0 signal by the action of NOT circuit 114 for resetting to zero the contents of clock pulse counters 92, 93 and 94. 

1. Apparatus for classifying and counting sheets comprising:
 1. conveyor means for conveying said sheets in a predetermined direction;
 2. a gate positioned at an intermediate point of said conveyor means for deflaecting said sheets away from said predetermined direction;
 3. sheets detecting means positioned at an intermediate point of said conveyor means for generating a signal when it detects said sheet;
 4. a plurality of classification receivers adapted to receive said sheets of different classes conveyed by said conveyor means;
 5. check means for determining the classes of said sheets which are to be collected in the corresponding classification receivers, said check means generating classification signals corresponding to said classes;
 6. gate driving means responsive to said classification signals and to the signal generated by said sheet detecting means;
 7. first counting means associated with said classification receivers for counting the number of sheets collected in the respective classification receivers;
 8. second counting means for adding the numbers of the sheets collected in the respective classification receivers;
 9. a comparator for comparing the sum of the numbers of the sheets counted by said second counting means with a preset number of sheets for determining whether the sum and the preset number coincide with each other or not;
 10. third counting means of the number equal to the number of said classification receivers for counting the number of sheets counted by said first counting means and collected in the respective classification receivers when said comparator determines that said sum coincides with said preset number;
 11. count control means for controlling the operation of said second and third counting means, and
 12. timing means for timing the operation of said third counting means.
 2. a gate positioned at an intermediate point of said conveyor means for deflaecting said sheets away from said predetermined direction;
 2. An apparatus according to claim 1 which further includes comparators for respective receivers which determine whether the numbers of sheets received in respective classification receivers and counted by said first counting means coincide or not with the numbers of the classification signals generated by said detector means corresponding to said sheets.
 2. said classification receivers are located at the ends of said first and second conveyor sections respectively;
 3. said sheet detector means comprises a source of light and a photoelectric converting element disposed to receive said light;
 3. An apparatus according to claim 2 wherein said comparator comprises a classification signal counter for counting the classification signals of the sheets which are checked by said check means and classified to be received in a predetermined classification receiver, a comparator for comparing the count of said classification signal counter and the number of sheets counted by said first counting means and collected in respective classification receivers, and means responsive to the output from said comparator for determining whether said compared count and said number coincide with each other or not.
 3. sheets detecting means positioned at an intermediate point of said conveyor means for generating a signal when it detects said sheet;
 4. a plurality of classification receivers adapted to receive said sheets of different classes conveyed by said conveyor means;
 4. An apparatus according to claim 3 wherein said means comprises a NAND circuit input terminals connected to receive the output signal from said comparator for comparing the numbers of sheets collected in respective receivers and a reference signal, and an output terminal connected to an alarm.
 4. said check means includes a check circuit to detect at least one of the features of the sheets including the width, thickness, codes, marks, numerals and pattern printed thereon for determining a classification receivers in which a sheet being checked is to be received and for generating a classification signal as a result of the check;
 5. said gate driving means comprises a switch element which operates upon receiving said classification signal from said check circuit and a signal from said gate detecting means, a switching circuit controlled by a signal from said switch element, and a relay operated by said switching circuit;
 5. An apparatus according to claim 1 which further includes means for classifying said sheets collected in said respective classifying receivers into bundls for collecting the same in corresponding bundle receivers.
 5. check means for determining the classes of said sheets which are to be collected in the corresponding classification receivers, said check means generating classification signals corresponding to said classes;
 6. gate driving means responsive to said classification signals and to the signal generated by said sheet detecting means;
 6. said counting means comprises sheet detecting means for detecting the sheets which are to be received in respective receivers, and for generating signals when detecting said sheets, and counters for counting said signals from said sheet detecting means;
 6. An apparatus according to claim 5 which further includes duplicate addition preventing means which prevents a fractional number of said sheets smaller than a definite number from being added to the number of sheets which are reclassified when certain number of sheets are stopped on their way toward said classification receivers and these stopped sheets and the fractional number of sheets remaining in a classification receiver are removed and subjected to a reclassification operation.
 7. An apparatus according to claim 5 wherein said sheet bundle classifying means comprises a conveyor for conveying said sheet bundles in a given direction; means for discharging said sheet bundles onto said conveyor from said classification receivers, means responsive to said discharge of said sheet bundles for generating classification signals; a sheet bundle detector including a source of light and a photoelectric converting element disposed to receive said light; a gate associated with said conveyor for deflecting said sheet bundles from said conveyor; a plurality of sheet bundle receivers associated with said conveyor for receiving sheet bundles of different classes; a plurality of switching means of the number corresponding to the types of said classification signals, said switching means being connected to operate in response to the classification signals from said classification signal generator and the output signal from said sheet bundle detector; and gate control means responsive to the output signal from said switching means; and gate operating means responsive to the output signal from said gate control means.
 7. said count control means comprises a clock pulse generator; clock pulse pass control means for controlling the passage of the clock pulse generated by said clock pulse generator; a plurality of pulse inhibitors of the same number as said receivers for successively controlling the passage of the pulses passed through said clock pulse pass control means; a plurality of clock pulse counters associated with said clock pulse inhibitors for counting the clock pulses passed through said clock pulse inhibitors; and a plurality of comparators associated with said clock pulse counters for comparing the counts of said clock pulse counters with the numbers of sheets for respective classification receivers counted by said first counting means;
 7. first counting means associated with said classification receivers for counting the number of sheets collected in the respective classification receivers;
 8. second counting means for adding the numbers of the sheets collected in the respective classification receivers;
 8. said second counting means comprises clock pulse control means for controlling the passage of the clock pulses passed through said plurality of clock pulse inhibitors; and an addition counter for counting the number of clock pulses passed through said clock pulse control menas;
 8. An apparatus according to claim 7 wherein said sheet bundle classifying means comprises a plurality of sheet bundle detectors disposed along said conveyor; wherein said switching means comprises a plurality of switch elements of the same number as said sheet bundle detectors, said switch elements being connected to receIve outputs from corresponding sheet bundle detectors, the first switch element being connected to receive the classification signal from said classification signal generator, the last switch element being connected in said gate control means for operating the same, said first switch element operating when it receives said classification signal and the output signal from said sheet bundle detector, and another switching elements operating sequentially when they are subsequently supplied with the output signals respectively from said sheet bundle detectors.
 9. An apparatus according to claim 8 wherein each of said switching elements comprises a plurality of J - K type flip-flop circuits, each having first and second output terminals on which ''''1'''' and ''''0'''' outputs are produced when set, the first and second output terminals of the first stage J - K type flip-flop circuit being connected to the J and K terminals respectively of the second stage J - K type flip-flop circuit, the J and K terminals of said first J - K type flip-flop circuit being connected to receive the classification signal from said classification generator, the first and second output terminals of the last stage flip-flop circuit being connected to said gate operating means for actuating the same and the terminals T of respective flip-flop circuit being connected to receive the output signals respectively from said sheet bundle detectors.
 9. a comparator for comparing the sum of the numbers of the sheets counted by said second counting means with a preset number of sheets for determining whether the sum and the preset number coincide with each other or not;
 9. said first counting means comprises clock pulse pass control means for controlling the passage of the pulses passed through said clock pulse inhibitors and a counter for counting the pulses passed through said pulse pass control means thereby determining the sum of said sheets collected in the respective receivers;
 10. said timing means comprises a delay circuit having two delay times, and a reset signal generator; and
 10. third counting means of the number equal to the number of said classification receivers for counting the number of sheets counted by said first counting means and collected in the respective classification receivers when said comparator determines that said sum coincides with said preset number;
 10. An apparatus according to claim 9 wherein the switching element of said switching member further includes switch operation check means.
 11. An apparatus according to claim 10 wherein said switch operation check means comprises a first AND circuit having input terminals connected to receive the output from said first output terminal of the switch element of one switching member, the output from the first output terminal of the switch element of the other switch member, and the output from said sheet bundle detector; a second AND circuit having input terminals connected to receive the output from the secone output terminal of the switching element of said one switching member, the output from the second output terminal of said switch element of said other switching means and the output from said sheets bundle receuver; and an OR circuit having input terminals connected to receive the outputs from said first and second AND circuits and an input terminal connected to an alarm device.
 11. count control means for controlling the operation of said second and third counting means, and
 11. said sum comparator comprises a comparator circuit for comparing the sum and control means for controoing the operation of said sum comparator circuit.
 12. timing means for timing the operation of said third counting means.
 12. An apparatus according to claim 7 wherein said gate control means comprises a switching circuit connected to be operated by the output signal from said gate operation control means, and a relay controlled by said switching circuit.
 13. An apparatus according to claim 7 wherein said sheet bundle classifying means comprises at least two sheet bundle receivers, a gate, and two switch members; and wherein said gate operation control means comprises two switch elements, one of said element having an output terminal which produces a ''''1'''' output when set and the other seitch element having an output terminal which produces a ''''0'''' output when set, an AND circuit connected to the output terminals of said two switch elements, a set-reset type flip-flop circuit having a set terminal connected to the output terminal of said flip-flop circuit, and first and second output terminal on which a ''''1'''' and a ''''0'''' outputs are produced when said flip-flop circuit is set, said first output terminal being connected to said gate operating means.
 14. An apparatus according to claim 13 wherein said sheet bundle classifying means further includes gate operation checking means which checks the operation of said gate.
 15. An apparatus according to claim 13 wherein said gate operation checking means comprises a gate position detector and a gate operation checking means.
 16. An apparatus according to claim 15 wherein said gate position detector comprises a micro-switch, disposed to be closEd when said gate is positioned in a position in which it permits free passage of said sheet bundle carried by said conveyor, and wherein said gate operation checking means comprises a first AND circuit having a first input terminal connected to said micro-switch and a second input terminal connected to the second output terminal of said set-reset type flip-flop circuit of said gate operation control means; a second AND circuit having a first input terminal connected to said micro-switch through an inverter, and a second input terminal connected to the first output terminal of said setreset type flip-flop circuit; and an OR circuit having input terminals connected to receive the outputs from said first and second AND circuits.
 17. An apparatus according to claim 5 wherein said duplicate addition preventing means comprises a first detector adapted to detect normal sheets; a normal sheet counter for successively counting the outputs from said counter, said normal sheet counter setting a predetermined value; a second detector for detecting the normal sheets collected in a corresponding receiver, a first counter associated with said receiver for successively counting the outputs from said second detector, said first counter baing set when its count reaches a predetermined value for commencing a new counting cycle; a memory for storing a fraction of the count of said counter which is smaller than a predetermined number; a third detector which detects discharge of the bundle of the sheets of said predetermined number from said receiver, a second counter responsive to the output from said third detector for counting the number of said sheet bundles discharged from said receiver; and a subtractor for subtracting said fraction stored in said memory from the count of said second counter, said subtractor setting the result of subtraction in said normal sheet counter.
 18. An apparatus according to claim 1 wherein;
 19. An apparatus according to claim 18 wherein a single J - K type flip-flop circuit having terminals J, K and T is provided for a first gate, said terminal J being connected to receive the classification signal from said check circuit, said terminal K being connected to receive an inverted signal of said classification signal, said terminal J being connected to receive detect signal from detecting means adapted to count the number of all sheets to be collected in respective classification receivers, and said J - K type flip-flop circuit being connected to said switching circuit for applying an output thereto, and wherein n J - K type flip-flop circuits, each having terminals J, K and T, are provided for n-th gate (excluding the first gate), the terminal J of the first flip-flop circuit being connected to receive the classification signal from said check means, the terminal K being connected to receive an inverted signal of said classification signal, the terminal J being connected to receive a signal from detecting means which counts the number of all sheets to be collected in respective receivers, the ''''1'''' output signals and the ''''0'''' output signals from said J - K type flip-flop circuits being supplied sequentially to the terminals J and K of up to the nth J - K type flip-flop circuits, the terminal J of up to the nth J - K type flip-flop circuits being connected to receive detect signals from detecting means provided before said gates (excluding the first gate), and the nth J - K flip-flop circuit being connected to supply the output signal thereof to said switching circuit.
 20. An apparatus according to claim 18 wherein said clock pulse pass control means of said counting control means comprises a set-reset type flip-flop circuit including a set terminal, a reset terminal, a first output terminal on which a ''''1'''' output is produced when said flip-flop circuit is set and a second output terminal on which an ''''1'''' output is produced when said flip-flop circuit is reset; a J - K type flip-flop circuit including terminals J, K and T and first and second output terminals, said J - K type flip-flop circuit producing a ''''1'''' output on said first output terminal when it is reset and a ''''1'''' output on said second output terminal when set, said first output terminal being connected to said terminal J, said second output terminal being connected to said terminal J and said terminal T being connected to receive a signal from said first comparator means, a first NAND circuit with input terminals connected to the second output terminal of said set-reset type flip-flop circuit and to the second output terminal of said J - K type flip-flop circuit; and a second NAND circuit with input terminals connected to the output of said first NAND circuit and to the output of said clock pulse generator, said second NAND circuit being connected to said clock pulse inhibitor to supply the output thereto, and wherein said clock pulse inhibitor comprises a plurality of NAND circuits, the NAND circuit corresponding to the first receiver having a input terminal connected to receive the output pulse from said pulse pass control member and the output signal from said sheet number comparator associated with said first receiver and an output terminal connected to said clock pulse counter, said NAND circuits passing the clock pulses from said clock pulse pass control means until said sheet number comparoator generates a coincidence signal; and wherein the NAND circuit associated with the nth receiver (excluding the first receiver) having input terminals connected to receive the output pulse from said clock pulse pass control means, the output signal from said sheet number comparator associated with said nth receiver, and the output signal from the sheet number comparator associated with the (n - 1)th receiver, and an output terminal connected to said clock pulse counter, said NAND circuit passing the clock pulse from said clock pulse pass control means when said sheet number comparator associated with said (n - 1)th receiver generates said coincidence signal.
 21. An apparatus according to claim 18 wherein said clock pulse control means of said second counting means comprises a first NAND circuit having an input connected to receive the output pulses from said plurality of clock pulse inhibitors; and a second NAND circuit having input terminals connected to receive the output from said first NAND circuit and the output from the second output terminal of the J - K type flip-flop circuit of said clock pulse pass control means and an output terminal connected to said sum counter.
 22. An apparatus according to claim 18 wherein the pulse pass control means of said third counting means includes NAND circuits associated with respective clock pulse inhibitors, each NAND circuit having input terminals connected to receive the output signal from a corresponding clock pulse inhibitor, and the output from the J - K type flip-flop circuit of said clock pulse pass control means, and an output terminal connected to said sum counter for counting the sum of the numbers of said sheets collected in the respective receivers.
 23. An apparatus according to claim 18 wherein the delay circuit of said timing means comprises two serially connected monostable malutivibrators, the first stage monostable multivibrator having a set terminal and first and second output terminals on which a ''''1'''' and a ''''0'''' output signals are produced respectively when said first stage monostable multivibrator is set, said set terminal being connected to receive the output from said sum comparators, the first output terminal of said first stage monostable multibibrator being connected to the set terminal of the second stage monostable multivibrator, said second stage monostable multivibrator having a first output terminal on which a ''''1'''' output is produced when said second stage monostable multivibrator is set, said first output terminal being connected to the terminal T of said J - K type flip-flop circuit and the second output terminal of said first stage monostable multivibrator being connected to the reset terminal of said set-reset type flip-flop circuit and to said reset signal generator; and where said reset signal generator comprises a first NAND circuit having input terminals connected to receive the output signal from the operation control member of said comparator means, and the output signal from the first output terminal of said J - K type flip-flop circuit, and an output terminal for providing an output for resetting said J - K type flip-flop circuit and said sum counter, and a second NAND circuit having input terminals connected to receive the output signal from said first NAND circuit and the output signal from said second output terminal of said first stage monostable multivibrator of said delay circuit, and an output terminal connected to said clock pulse counter for resetting the same.
 24. An apparatus according to claim 18 wherein said operation control means for said comparator means comprises a NAND circuit having input terminals connected to receive output signals from said respective sheet number comparators, and an output terminal; and an AND circuit having input terminals connected to receive the output from said NAND circuit and the output from the second output terminal of said J - K type flip-flop circuit and an output terminal connected to said comparator for comparing the sum of the number of said sheet for resetting said comparator. 